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YGV639 vc1e video controller 1 with enhanced functions YGV639 catalog catalog no.: lsi-4gv639a30 2010.5 outline YGV639 (hereafter referred to as ?vc1e,? its func tion name) is the display controller which makes it easier to create a highly colorful graphic im age in a low-cost system configuration. vc1e, having a build-in digital video decode, allows characters, lines, and graphic icons (hereafter, called ?sprite?) to be superimposed over cvbs signal from a ccd camera. it is possible to represent moving images like animat ion even through a serial port communication, and vc1e realize impressively higher colorful picture expression under an equivalent cpu control load as that of a low-cost osd controller. a pattern memory, up to 512m bits (64m bytes), for storing font data or bitmap display data that are used for a sprite, is connectable to vc1e. a complicated display control program needed to be developed for the conventional graphic controller; however, vc1e allows sprites to be easily displa yed only by rewriting the attribute table for display. vc1e has a build-in line memory for display. for this reason, an external vram becomes unnecessary and this allows a system to be built with fewer components. with recent increase of safety awareness, in-vehic le video cameras are becoming more and more popular. vc1e is best suited for such as parking-support syst em as would perform superimposition of car-width lines over a video camera footage. vc1e measures up to the in-vehicle temperature guar antee conditions and can be used also for in-vehicle ecu.
YGV639 2 how vc1e creates an image plane image plane constitution the screen which vc1e displays consists of 341 hierarchical images, called a layer, one backdrop plane, and a border plane w ith a single color. any one among sprite, two or more lines, and text can be selected in one layer. one sprite, one character string, and lines (up to 510) can be displayed on one layer. (1) sprite (2) two or more lines (3) character string abc the display priority order of layers is in order of a la yer, a backdrop plane, and a border plane fr om the top. when a layer or an external video image is not displayed, the border color which is set for the border plane is displayed. also when sprites are overlaid and displayed, a lower image comes to appear by setting the surroundings of sprites as a transparent color. mo reover, images can also be overlaid as translucent. this is called alpha blending.
YGV639 3 features display function monitor supported tft liquid crystal display (digital rgb connection) or a display equipment with the equivalent i/f monitor resolution programmable for ntsc, pal, qvga, wqvga, vga, wvga, svga build-in lcd timing controller function display plane functions layered structure up to 341 layers and up to one backdrop plane layer displays sprites, lines and texts by layers alpha-blending control by pixel (alpha by pixel) layer picture quality adjustment function (contrast, brightness) animation by a macro command function graphic generation function sprite sprite display: up to 341/field size: 8x8 to 512x512 dots, horizontally and vertically independent selection (in 8-dot unit) 2, 16, 32, 64, or 256 palette colors in 64k colors, 65536-color natural picture display by 16-bit rgb natural picture display flip function (vertically and horizontally) scaling function alpha blending in pixels anti aliasing function in the outline part text specifies a font type fo r each character string supports variable-width fonts such as proportional fonts scaling function supports anti aliasing font line drawing direct drawing by specification of start/end po int coordinates (pattern data is not needed) configurable line display up to 510 lines/field display color: 32768-color (rgb555) specification or palette index (10 bits) specification available line width: 1 dot to 16 dots (in dot unit) anti aliasing drawing function video picture input built-in digital video decoder inputs composite video signals in ntsc/pal directly and then converts them into digital rgb contrast, brightness, color saturation and hue adjustment function color killer function, video input detection function video picture input display function scaling function (a function to adjust the resolution of the input image to the display resolution, not a zooming function) mirror inversion function (only horizontal direction) others cpu interface 8-bit parallel or serial connection indirect mapping to the built-in registers and tabl es through the access ports pattern memory interface up to 512m bits (64m bytes), 8-bit/16-bit bus width mask rom, sram, and nor type flash-memory connectable configurable access timing by the system clock cycle device specifications 144-pin lead-free lqfp package ( YGV639-vz) cmos: 3.3v power supply (built-in regulator for core voltage[1.8v]) variable cpu interface power supply (3.3v to 5v) operation temperature range -40 to +105
YGV639 4 block diagram sprite & text rendering processor sprite & text plane generator frame data controller monitor i/f dr5-0 dg5-0 db5-0 hcsync_n vsync_n blank_n dotclk clkv starth startv loadh pol outenv tcone crtc general ta b le color palette registers pattern memory interface clock gen. cpu interface clock xin xout dtckin dtcks_n pllctl3-0 pattern memory i/f md15-0 ma25-0 moe_n mwe_n rahz_n cpu i/ f d7-0 ps2-0 cs_n rd_n wr_ n wai t _ n ready_n int_n sdin sdout scs_n sclk ser_n reset_n f line buffer line plane generator line rendering processor to all blocks analog video input vinp vinm vrefp vrefn vref0 analog front end video decoder line buffer (video display use) to al l blocks macro command module video signal controller
YGV639 5 example of system configuration an example of a system configuration with vc1e is shown below. vc1e pattern memory ma25-1 md15-0 mwe_n moe_n pattern memory interface ma25-1 md15-0 mwe_n moe_n rahz_n cpu interface rd_n wr_n cs_n ps2-0 d7-0 wa i t _ n ready_n int_n cpu rd_n wr_n cs_n address data wa i t _ n ready_n int_n lcd monitor red green blue vsync_n hcsync_n clock monitor interface dr5-0 dg5-0 db5-0 vsync_n hcsync_n dotclk blank_n video interface vinp vinm vrefp vrefn vref0 video camera clock xin xout pllctl3-0 dtckin dtcks_n regulator vddin vddcore vout18 power pllvdd vdd33 avdd vdd5 test signals xtest2-0 test_reg 3.3v digital power 3.3v digital power 3.3v analog power 3.3~5v cpu interface power
YGV639 6 pin functions pin table cpu interface (23) pin name num. i/o function attribute power supply group level drive d7-0 8 i/o cpu data bus 5v tolerant vd5 cmos 4ma ps2-0 3 i cpu port selection 5v tolerant vd5 cmos cs_n 1 i chip select (dual-purpos e pin) 5v tolerant vd5 cmos rd_n 1 i read strobe (dual-purpose pin) 5v tolerant vd5 cmos wr_n 1 i write strobe (dual-purpose pin) 5v tolerant vd5 cmos wait_n 1 ot cpu bus wait (3-state output) (dual-purpose pin) 5v tolerant vd5 cmos 4ma ready_n 1 ot cpu bus ready (3-state output) 5v tolerant vd5 cmos 4ma int_n 1 od interrupt (open drain) 5v tolerant vd5 cmos 4ma ser_n 1 i cpu interface selection - vd3 cmos scs_n 1 i serial interface chip select (dual-purpose pin) 5v tolerant vd5 cmos sdin 1 i serial interface data input (dual-purpose pin) 5v tolerant vd5 cmos sdout 1 ot serial interface data output (3-state output) (dual-purpose pin) 5v tolerant vd5 cmos 4ma sclk 1 i serial clock input (dual-purpose pin) 5v tolerant vd5 cmos reset_n 1 i$ reset tolerant vd3 cmos pattern memory interface (45) pin name num. i/o function power supply group level drive md15-0 16 i/o pattern memory data bus vd3 lvcmos 4ma ma25-0 26 ot pattern memory address bus (3-state output) vd3 lvcmos 4ma moe_n 1 ot pattern memory output enable (3-state output) vd3 lvcmos 4ma mwe_n 1 ot pattern memory write strobe (3-state output) vd3 lvcmos 4ma rahz_n 1 i pattern memory high- impedance switchi ng vd3 lvcmos video interface (5) pin name num. i/o function attribute power supply group level drive vinp 1 i analog video input analog avdd analog vinm 1 i test input pin analog avdd analog vref0 1 o adc referenc e pin analog avdd analog vrefp 1 o plus refere nce voltage pin for adc analog avdd analog vrefn 1 o minus reference voltage pin for adc analog avdd analog
YGV639 7 monitor interface (29) pin name num. i/o function power supply group level drive dr5-0 6 o digital video: r output vd3 lvcmos 2ma dg5-0 6 o digital video: g output vd3 lvcmos 2ma db5-0 6 o digital video: b output vd3 lvcmos 2ma vsync_n 1 o vertical synchronization signal output (dual-purpose pin) vd3 lvcmos 2ma hcsync_n 1 o horizontal / composite synchronization signal output (dual-purpose pin) vd3 lvcmos 2ma blank_n 1 o blank signal output pin (dual-purpos e pin) vd3 lvcmos 2ma dotclk 1 o dot clock output vd3 lvcmos 2ma clkv 1 o vertical clock output (d ual-purpose pin) vd3 lvcmos 2ma starth 1 i/o horizontal start signal output (dual-purpose pin) vd3 lvcmos 2ma startv 1 o vertical start signal output (dual-purpose pin) vd3 lvcmos 2ma loadh 1 o horizontal load signal outpu t (dual-purpose pin) vd3 lvcmos 2ma pol 1 o polarity inversion output (dual-purpose pin) vd3 lvcmos 2ma outenv 1 o output enable signal (dual-purpose pin) vd3 lvcmos 2ma tcone 1 i timing controller select pin (with a pull-down resistor) vd3 lvcmos clock (8) pin name num. i/o function power supply group level drive xin 1 i reference clock input pin vd3 xout 1 o crystal connection pin vd3 dtckin 1 i dot clock input pin vd3 lvcmos dtcks_n 1 i dot clock input selection pin vd3 lvcmos pllctl3-1 3 i/o pll multiplication ratio setting pin (dual-purpose pin) vd3 lvcmos 2ma pllctl0 1 i pll multiplication ratio setting pin vd3 lvcmos for device (43) pin name num. i/o function attribute power supply group level drive xtest2-0 3 i test pin - vd3 lvcmos vdd33 11 - digital power supply pin - - vdd5 1 - cpu interface power supply pin - - vss 14 - digital vss pin - - pllvdd 1 - pll power supply pin - - avdd1, avdd2 2 - analog front end power supply pin - - avss 2 - analog front end vss pin - - ocpen 1 i reset of the over-current protection circuit over-current protection circuit enable/disable switching pin 5v tolerant vd5 cmos test_reg 1 i over-current protection circuit enable/disable control 5v tolerant vd5 cmos ocp_n 1 o over-current detection output - vd5 cmos 4ma vddcore 3 - capacitor connection pin for core power supply - vddin vout18 1 - 1.8v digital power supply output - vddin vddin 2 - 3.3v input for core power supply (1.8v) - - note: vc1e has no pull-up resistors. pull up a pin externally as necessary. the meaning of a sign of [i/ o] column is as follows: i: input pin i$: schmitt trigger input pin o: output pin ot: 3-state output pin od: open-drain output pin
YGV639 8 the meaning of [attribute] column is as follows: analog: analog pin tolerant: tolerant attribute represents that curr ent does not flow to a power supply pin from the voltage-applied pin, when voltage higher than supply voltage is applied to the pin. however, since this pin cannot withstand 5v, it is n ecessary to make the voltage difference between the pin and the power supply voltage less than 3.6v. therefore, voltage exceeding 3.6v (maximum of recommended operation voltage) cannot be applied to it without the supply of power (supply voltage = 0v). 5v tolerant: 5v tolerant attribute means the pin has a withstand voltage of 5v. that is, 5v can be applied to this pin when supply voltage is 0v. dual-purpose pin sharing cpu interface pins vc1e supports the two types of cpu interfaces: serial and parallel interfaces. pins are shared by the interfaces as follows: pin name parallel interface (ser_n=h) serial interface chip select (ser_n=l) d7-0 d7-0 unused ps2-0 ps2-0 unused cs_n cs_n scs_n rd_n rd_n sdin wr_n wr_n sclk wait_n wait_n sdout ready_n ready_n unused int_n int_n int_n sharing timing-controller pins vc1e has a built-in lcd timing controller and this function can be enabled by tcone pin setting. the following pins are shared depending on whether the timing controller is enabled or disabled. pin name timing controller disabled (tcone=l) timing controller enabled (tcone=h) dr5-0 dr5-0 dr5-0 dg5-0 dg5-0 dg5-0 db5-0 db5-0 db5-0 dotclk dotclk dotclk hcsync_n hcsync_n clkv vsync_n vsync_n pol blank_n blank_n startv pllctl3 pllctl3 loadh pllctl2 pllctl2 starth pllctl1 pllctl1 outenv
YGV639 9 pin arrangement vdd33 md0 md8 md1 md9 vss md2 md10 md3 md11 vdd33 md4 md12 md5 md13 vss md6 md14 vddcore md7 md15 vdd33 moe_n mwe_n ma25 ma24 vss ma23 ma22 ma21 ma20 vdd33 ma19 ma18 ma17 ma16 rahz_n dr0 dr1 dr2 vss dr3 dr4 dr5 dg0 vdd33 dg1 dg2 dg3 dg4 vss dg5 db0 vddcore db1 db2 vdd33 db3 db4 db5 vsync_n / pol vss hcsync_n / clkv blank_n / startv dotclk vdd33 dtcks_n pllctl3 / loadh pllctl2 / starth pllctl1 / outenv pllctl0 ser_n vss ma15 ma14 ma13 ma12 vdd33 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 vdd33 ma3 vddcore ma2 ma1 ma0 vss xin xout vdd33 dtckin pllvdd n .c. tcone vss avss vrefp vrefn vref0 av d d 2 av d d 1 vss vinm vinp av s s int_n vss ready_n vdd5 wait_n / sdout vss d7 d6 d5 d4 d3 d2 d1 d0 vss ocp_n test_reg ocpen vddin vout18 vddin vdd33 ps0 ps1 ps2 vss rd_n / sdin wr_n / sclk cs_n / scs_n xtest2 xtest1 xtest0 reset_n 1 36 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 vc1e top view note: n.c. (pin 45) is a no connection pin, with only lead frame, and no bonding wire is connected.
YGV639 10 description of pin function power supply digital power supply pins vdd33, vddin, vss (power supply) the power supply pins for the internal digital circuit. supply 3.3v to vdd33 and vddin pins. supply the ground level to vss pins. it is recommended to decouple vdd33 and vddin with respect to the ground through a high-frequency ceramic capacitor. the de coupling capacitor should be positioned between vdd33 and vss, vddin and vss as close to the device as possible so th at the wiring length becomes the shortest. power supply pin for pll pllvdd (power supply) this is the analog power supply pin for vco of the built-in pll. connect vout18 pin to pllvdd pin. connect a decoupling capacitor between this pllvdd and the vss (pin 43). power supply pins for analog front end avdd1, avdd2, avss (power supply) this is the analog power supply pin for the built-in analog front end. supply 3.3v to avdd1 and avdd2 pins. supply the ground level to avss pins. these power supplies should be separated from the other power supplies. it is recommended that this pin should be decoupled by a high-frequency ceramic capacitor to the analog ground. a decoupling capacitor should be positioned between avdd1 (pin 37) and avss (pin 34), avdd2 (pin 38) and avss (pin 42) as close to the device as possible so that the wiring length becomes shortest. inside the lsi, avdd1 is connected to an ad converter and avdd2 is connected to a clamping circuit or a reference voltage circuit. avdd1 generates about 27 mhz switching noise. therefore, it is recommended to take measures, such as insertion of different ferr ite beads to avdd1 and avdd 2, so that noise may not input to avdd2 through avdd1. power supply pin for cpu interface vdd5 (power supply) this is the power supply pin for the level shifter of cpu interface. it is possib le to input 3.3v to 5v according to cpu interface voltage. connect a decouplin g capacitor between this pin (vdd5) and vss pin. system reset reset pin reset_n (schmitt trigger input) this is the power-on reset input pin. the reset signal must be input for a given time after power on. this pin is low active. the pin uses a schmitt trigger type buffer
YGV639 11 clock there are three clocks which are used in vc1e. (1) dot clock : clock for picture display and picture data output. (2) system clock : internal clock (about 81mhz) for picture processing in vc1e. (3) decoder clock : internal clock (about 27mhz) that is used when decoding analog video signals. these three clocks can be generated from a single crystal resonator. pll reference clock crystal connection pins xin (input), xout (output) vc1e oscillates clocks by connecting a crystal resonator to xin and xout pins. when using the externally-oscillated clock, input it to xin pin. in this case, nothing should be connection to xout pin. when generating a dot clock, system clock and decoder clock from a single clock input, connect a crystal resonator of the same frequency as that of the dot clock to this xin pin or input the clock. the frequency that can be oscillated with xin and xout pins is 6mhz to 30mhz. the clock frequency that can be input to xin pin ranges from 6mhz to 40mhz. below is shown the external circuit for the clock oscillation with a crystal resonator. crystal resonator rf xout(pin49) xin(pin50) c1 c2 rd vss(pin51) vdd33(pin48) 3.3v board gnd c1, c2: external load capacity rf: feedback resistor rd: damping resistor ? reference values of the oscillator circuit constants crystal resonator kyocera kinseki cx8045gb 8mhz kyocera kinseki cx8045gb 14mhz rf 1m 1m rd 1.6k 820 c1, c2 12pf 12pf note: the above constants do not always guarantee the oscillation as they are the reference values based on the evaluation under the particular circumstance. for actual application, please ask the resonator?s manufacturer to evaluate the resonator with it mounted on a board. in order to secure stable operation of the oscillati on circuit, it is recommended to take the following measures for preventing noise. (1) lsi and crystal resonator, etc. should be placed as close to each other as possible to shorten the length of wiring. (2) gnd of the oscillation circuit must be directly connected to vss(pin51) of the lsi. (3) the oscillation circuit must be separated from a wiring pattern in which a large current flows.
YGV639 12 (4) connect a decoupling capacitor betw een vdd33(pin48) and vss(pin51). (5) board?s gnd pattern must be wide enough to prevent the interference from other signals. connect this gnd to vss(pin51). vc1e?s electrical characteristics were determined based on the assumption that a x'tal resonator is to be connected to xin/xout or x'tal oscillator is to xin. therefore, it is recommended to use a crystal resonator or crystal oscillator. use a x'tal resonator or x'ta l oscillator with the allowable frequency deviation (including temperature char acteristics) of 100ppm. ? ceramic resonator if using a ceramic resonator, the following points should be considered. use a ceramic resonator with the same jitter pe rformance as that of a crystal resonator. ceramic resonators have relatively bigger allowable frequency deviation and frequency temperature characteristics than th ose of a crystal resonator. such variation is not considered in the design; theref ore, the system clock frequency should be within the range of the specification (83.16mhz or less for vc1e) even if the frequency varies. dot clock input pin dtckin (input) when a dot clock is present in the system, this dot clock can be directly input to dtckin pin as a dot clock. the pin input is enabled when dtcks_n=?l.? when dtcks_n=?h,? a dot clock is generated by the clock input to xin pin. at this time, connect vdd33 or gnd to dtckin pin. a clock frequency up to 40mhz can be input into dtckin pin. dot clock input select pin dtcks_n (input) this is the pin to select which one of either xin or dtckin pin should be used for supplying the internal dot clock. this pin is low active. be sure to determine the level of the input signal to this pin during the reset (reset_n pin=?l?) at power-on, and do not change th e state while the power has been already established. pll control pin pllctl3-0 (input) these pins set a multiplication ratio of the built-in pll that generates a system cloc k. be sure to determine the level of the input signals to the pins during the reset (reset_n pin=?l?) at power-on, and do not change the state while the power has been already established. pllctl3-1 are dual-purpose pins for loadh, starth, and outenv, respectively. when using a built-in timing controller, it functions as loadh, sharth, and outenv.
YGV639 13 cpu interface although in vc1e either 8- bit asynchronous parallel or synchronous serial interface can be selected, pins are shared by both interfaces. cpu data bus d7-0 (input and output) when using 8-bit parallel interface, connect these pins to the cpu data bus. d7-0 serve as output pins when both cs_n and rd_n pins are asserted (?l? level input), otherwise, it serves as input pins. pull up d7-0 pins outside the device as no pull-up resistors are provided. when using the serial interface, input ?h? or ?l? level to the pins. port select pins ps2-0 (input) internal port selection pins. connect the pins to the cpu address bus when 8-bit parallel interface is used. when using vc1e in serial interface, input ?h? or ?l? level to the pins. chip select pin cs_n (input) chip-select input pin when 8-bit pa rallel interface is selected. wr_n and rd_n pins are enabled when this signal is in active state. connect cs_n pin to the cpu's chip select pin for external devices. this pin is low active. this pin is a dual-purpose pin. when using the serial interface, it functions as scs_n pin. read strobe input pin rd_n (input) read strobe input pin when 8-bit parallel interface is used. this pin is low-active. this pin is a dual-purpose pin. when using the serial interface, it functions as sdin pin. write strobe input pin wr_n (input) write strobe input pin when 8-bit parallel interface is used. this pin is low active. this pin is a dual-purpose pin. when using the serial interface, it functions as sclk pin. cpu bus wait pin wait_n (3-state output) the bus wait signal is output when 8-bit parallel interface is used . use this pin and ready_n pin properly depending on cpu. this pin is a 3-state output. while ?h? level is input to cs_n pin, it becomes a hi gh impedance state. this pin is low active. pull up this pin outside the device as no pull-up resistor is provided. this pin is a dual-purpose pin. when using the serial interface, it functions as sdout pin. cpu bus ready pin ready_n (3-state output) the bus ready signal is outp ut when 8-bit parallel interface is used. use this pin and wait_n pin properly depending on cpu. this pin is a 3-state output. while ?h? level is input to cs_n pin, it becomes a high impedance state. this pin is low active. pull up ready_n pin outside the device as no pull-up resistor is provided.
YGV639 14 interrupt pin int_n (open drain output) an interrupt request signal is output. int_n signal is a sserted when a flag enabled by the internal register is set to ?1.? when the flag is reset by the writing to the flag bit or when the interrupt enable bit is set to ?0,? int_n signal is negated and becomes high impedance state. this pin is low active. since this pin is an open-drain output, a wired-or connection with similar interrupt signals can be made. pull up int_n pin outside the device as no pull-up resistor is provided. cpu interface select pin ser_n (input) cpu interface selection pin. when choosing the serial interface, set to ?l.? when choosing the parallel interface, set to ?h.? this pin is low active. an input signal level should be settled during the period of reset_n pin=?l? at power-on and must not be changed while the power is on. serial interface chip select input pin scs_n (input) this is used as the chip select input pin when seri al interface is selected. sdin and sclk pins become enabled when this signal is in active state. this pin is low active. this pin is a dual-purpose pin. when using th e parallel interface, it functions as cs_n pin. serial data input pin sdin (input) this pin is used as the serial data in put pin when serial interface is selected. this pin is a dual-purpose pin. when using th e parallel interface, it functions as rd_n pin. serial data output pin sdout (3-state output) this pin is used as the serial data outp ut pin when serial interface is selected. this pin is a dual-purpose pin. when using th e parallel interface, it functions as wait_n pin. serial clock input pin sclk (input) this pin is used as the serial clock in put pin when serial interface is selected. this pin is a dual-purpose pin. when using th e parallel interface, it functions as wr_n pin.
YGV639 15 pattern memory interface these pins are used for interface with a pattern memory connected to vc1e local buses. mask-rom, nor-type flash memory and sram, etc. ca n be connected as a pattern memory. pattern memory data bus md15-0 (input and output) data input-output bus for a pattern memory. when the data bus width of a pattern memory is 16 bits, connect an external memory to md15 -0. when the data bus width is 8 bits, connect an external memory to md7-0 and pull up md15-8. the data bus width of a pattern memory is set by the register (r#5: bw). md15-0 serve as output pins only fo r the write access to a pattern memory; otherwise, they serve as input pins. however, when the pattern memory bus is set to 8 bits, md15-8 serve as input pins, even in the write access. md15-0 pins become high impedance when rahz_n= ?l.? and, when core power supply is shut down with the activation of the over current protection circuit, this pin becomes high impedance due to the voltage decrease. it is recommended to connect an external pull-up resistor of 10k ? to 50k ? to this pin. pattern memory address bus ma25-0 (3-state output) address bus output pins for the pattern memory. when the data bus width of a pattern memory is 16 bits, connect it to ma25-1. when the width is 8 bits, connect it to ma25-0. when rahz_n is ?l? level or when core power supply is shut down by the overcurrent protection circuit in the internal regulator, ma25-0 pins become high impedance. pattern memory output enable pin moe_n (3-state output) pattern memory output enable pin. this pin is low active. when rahz_n is ?l? level, moe_n pin becomes high impedance. and, when core power supply is shut down with the activation of the over current protection circuit, this pin becomes high impedance due to the voltage decrease. it is recommended to a ttach an external pull-up resistor 10k ? to 50k ? to this pin. pattern memory write strobe output pin mwe_n (3-state output) writing enable output pin for pattern memory. this pin is low active. when rahz_n is ?l? level, mwe_n pin becomes high impedance. and, when core power supply is shut down with the activation of the over current protection circuit, this pin becomes high impedance due to the voltage decrease. it is recommended to attach an external pull-up resistor 10k ? to 50k ? to this pin. pattern memory high-impedance switching pin rahz_n (input) sets the interface pins for the pattern memory to high impedance. assert this pin to separate the pattern memory electrically from vc1e. this pin is low active.
YGV639 16 monitor interface these pins output picture data or timing signals to an external monitor. digital picture interface pins dr5-0, dg5-0, db5-0 (output) these pins output digital r, g, and b signals of display data in synchronization with dotclk. vertical synchronization signal output pin vsync_n (output) the vertical sync signal is output in synchronization with dotclk. this pin?s activation state is selectable by the register setting. when the register (r#6:revsy) is ?0?: low-active when the register (r#6:revsy) is ?1?: high-active this pin is dual-purpose pin. when using the built-in timing controller, it functions as pol. horizontal / composite synchronization signal output pin hcsync_n (output) horizontal or composite sync signal is output in synchronization with dotclk. which signal should be output is specified by the resistor (r#6: csyoe). this pin?s activation state is selectable by the register setting. when the register (r#6:revsy) is ?0?: low-active when the register (r#6:revsy) is ?1?: high-active this pin is dual-purpose pin. when using the built-in timing controller, it functions as clkv. blank signal output pin blank_n (output) a signal that indicates a blank period is output in synchronization with dotclk. this signal can be used when needing the signal (de) which indicates a display period in an lcd panel etc. this pin is dual-purpose pin. when using the built-in timing controller, it functions as startv. dot clock output pin dotclk (output) this pin outputs a dot clock. the dot clock used in vc1e is output. the following three ways are selectable. (1) outputs an input clock to xin pin as is or in frequency-divided form (2) outputs a pll output clock as is or in frequency-divided form (3) outputs an input clock to dtckin pin as is dotclk has the inversion output function. this is implemented by selecting the clock reversed by the group selector just before outputting an internal dot clock to dotclk pin. set dotclk inversion function so that it meets each signal's set-up/hold time regul ation of your monitor w ith respect to dotclk. this pin output optimizes the drive capability to qvga, dotclock frequency of approx. 6.36mhz. when using a dot clock frequency of approx. 20mhz or more, it is recommended to add a clock buffer to the board. and, when lcd?s input capacitance is large, the wavefo rm may get distorted; ther efore, check the waveform by using an actual terminal. vertical clock output pin clkv (output) when using the built-in timing controller, it outputs a vertical clock. this pin is dual-purpose pin. when not using the built-in timing contro ller, it functions as hcsync_n.
YGV639 17 horizontal start signal output pin starth (output) when using the built-in timing controller, it outputs a horizontal start signal. this pin?s activation state is selectable by the register setting. when the register (r#111: revsh) is ?0?: high-active when the register (r#111: revsh) is ?1?: low-active this pin is dual-purpose pin. when not using the built-in timing controller, it functions as pllctl2. vertical start signal output pin startv (output) when using the built-in timing controller, it outputs a vertical start signal. this signal?s activation state is selectable by the register setting. when the register (r#112: revsv) is ?0?: high-active when the register (r#112: revsv) is ?1?: low-active this pin is dual-purpose pin. when not using th e built-in timing controller, it functions as blank_n. horizontal load signal output pin loadh (output) when using the built-in timing controller, it outputs a horizontal load signal. this signal?s activation state is selectable by the register setting. when the register (r#111: re vlh) is ?0?: high-active when the register (r#111: revlh) is ?1?: low-active this pin is dual-purpose pin. when not using the built-in timing controller, it functions as pllctl3. polarity invert signal output pin starth (output) when using the built-in timing controller, it outputs a polar ity invert signal. this pin is dual-purpose pin. when not using the built-in timing co ntroller, it functions as vsync_n. output enable signal outenv (output) when using the built-in timing controller, it outputs an output-enable signal. this pin is dual-purpose pin. when not using the built-in timing controller, it functions as pllctl1. timing controller select pin tcone (input) this is a select pin for the built-in timing controller. if this tcone pin is connected to ?vdd33?, the timing signal to be output from a built-in timing controller will be output to a dual-purpose pin. an input signal level should be settled during the period of reset_n pin=?l? at power-on and must not be changed while the power is on. although a pull-down resistor is included, it is recommended to connect this pin to gnd when using it with tcone=l. when using with tcone=h, this pin should be connected to vdd33 without the resistor.
YGV639 18 power regulator pins for core vc1e has the built in regulator for core power supply. and over current protection circuit to detect a short circuit is also incorporated. over current protection circuit reset pin ocpen (input) enables/disables the operation of th e over current pr otection circuit. ?h? input: enable operation of over current protection circuit. ?l? input: disable operation of ov er current protection circuit. this signal shuts down the power supply regulator output temporarily when detecting an over-current condition. ocpen functions as the reset signal of the over curre nt protection circuit. when ?l? is input to ocpen, power is supplied again. over current protection circuit enable pin test_reg (input) this is the test pin for the over current protection circuit. normally, this pin should be used with it held to ?l.? output of over current detection state ocp_n (output) this signal indicates the state of the over current protection circuit. connect this pin to a cpu port etc. to monitor its state. ?l? output: the regulator shuts down the core power supply by detecting an over current condition. ?h? output: the regulator outputs the power as normal operation. ocp_n pin becomes ?l? level when the voltage of the core power supply output pin vout18 is low, such as at power-on or power supply recovery from the shutdown state due to overcurrent detection, etc. capacitor connection pin for core power supply vddcore the decoupling capacitor connection pins for core power supply. connect a 4.7 f ceramic capacitor between vddcore and gnd. put the capacitor as close to vddcore pin as possible. note: do not supply power to this vddcore pin. 1.8v power output pin vout18 (output) 1.8v-power-supply regulator output pin. connect it to pllvdd pin. connect a 4.7 f ceramic capacitor between vout18 and gnd. put the capacitor as close to vout18 pin as possible.
YGV639 19 analog front end analog video input vinp (input) analog video input pin. input composite video signals to this pin. vinp 47pf 0.22f 51 ? 75 ? video input avss (pin42) use laminated ceramic capacitors (capacitance toleran ce: 10%, temperature coe fficient: 15%) or those having higher characteristics. reference voltage pins for adc vrefp, vrefn, vref0 (output) these pins are for generating a reference voltage insi de analog front end. connect a capacitor externally. 2.2 f vrefn vre f0 vrefp 0.1f 0.1f 0.1f 0.1f use laminated ceramic capacitors (capacitance toleran ce: 10%, temperature coe fficient: 15%) or those of higher characteristics except for the 2.2 f capacitor. test differential input pin vinm (input) this is a test pin. this signal functions as a differential input pin of vinp input at the test. normally connect it to avss.
YGV639 20 other control pins for device test pin xtest2-0 (input) these are the test mode setting pins for device test. be sure to use them in the following setting. pin name xtest2 xtest1 xtest0 input level h h h note that if the device is used outside the specified level, the device itself or the system using it may be damaged significantly.
YGV639 21 electrical characteristics absolute maximum ratings items symbol rating unit note supply voltage (vdd5 pin) v dd5 -0.5 to +7.0 v 1 supply voltage (vdd33, vddin pin) v dd33 -0.5 to +4.6 v 1 analog supply voltage (avdd pin) v av d -0.5 to +4.6 v 1 pll supply voltage (pllvdd pin) v plvd -0.5 to +2.5 v 1 input pin voltage (vdd5 power supply pin) v i -0.5 to +7.0 v 1 input pin voltage (reset_n pin) v i -0.5 to vdd33+4.6 ( 5.5 max.) v 1 input pin voltage (vdd33 power supply pin other than reset_n) v i -0.5 to vdd33+0.5 ( 4.6 max.) v 1 input pin voltage (avdd power supply pin) v i -0.5 to avdd+0.5 ( 4.6 max.) v 1 output pin voltage (including vdd5 power supply, tolerant pin, and input/output pins) v o -0.5 to +5.5 v 1 output pin voltage (other vdd5 power supply pin) v o -0.5 to vdd5+0.5 ( 5.5 max.) v 1 output pin voltage (including vdd33 power supply pin and input/output pins) v o -0.5 to vdd33+0.5 ( 4.6 max.) v 1 output pin voltage (including avdd power supply pin and input/output pins) v o -0.5 to avdd+0.5 ( 4.6 max.) v 1 input pin current i i -20 to +20 ma output pin current i o -20 to +20 ma storage temperature t stg -50 to +125 note) refer to ? pin table? for the details of the power supply pin and the attribute. note 1) values are based on vss(gnd)=0v recommended operating condition items symbol min. typ. max. unit note power-supply voltage (vdd33, vddin pins) v dd33 3.0 3.3 3.6 v 1 analog power supply (avdd pins) v av d 3.0 3.3 3.6 v 1 pll power supply (pllvdd pins) v plvd 1.65 1.8 1.95 v 1, 2 cpu i/f power supply (vdd5 pins) v dd5 3.0 5.0 5.25 v 1 operating ambient temperature t op -40 105 3 note 1) values are based on vss(gnd)=0v. note 2) pllvdd pin should be connected to vout18 pin. no need to prepare an external 1.8v power supply. note 3) this value is estimated with the following conditions: four-layer substrate with the si ze of more than 100 mm 120 mm copper-thin film area ratio over 300% no solder applied between stage and substrate consumption current items conditions symbol min. typ max. unit note total power consumption p d 544 mw 1 consumption current breakdown vdd33, vddin i vdd 120 ma 1, 2 vdd5 c l =20pf v il =gnd v ih =v dd33 i vdd5 7.5 ma 1 avdd i av d 20 ma 1 note 1) consumption current and consumption pow er values are the values measured under the recommended operating condition. note 2) the current flowing through pllvdd pin is included in vdd33?s and vddin?s current values because it is generated by the internal regulator.
YGV639 22 dc characteristics items symbol min. typ. max. unit note low level input voltage xin pin v il -0.3 v dd33 0.3 v 1 power supply group ?vd3? input and i/o pins (except xin pin) v il -0.3 0.8 v 1,2 power supply group ?vd5? input and i/o pins at vdd5=3.0 to 3.6v v il -0.3 v dd5 0.2 v 1,3 power supply group ?vd5? input and i/o pins at vdd5=3.6 to 5.25v v il -0.3 0.8 v 1,3 high level input voltage xin pin v ih v dd33 0.7 v dd33 +0.3 v 1 power supply group ?vd3? input and i/o pins (except xin pin) v ih 2.0 3.6 v 1,2 power supply group ?vd5? input and i/o pins at vdd5=3.0 to 3.6v v ih v dd5 0.8 v dd5 +0.3 v 1,3 power supply group ?vd5? input and i/o pins at vdd5=3.6 to 5.25v v ih 2.0 5.25 v 1,3 note 1) values are based on vss(gnd)=0v. note 2) regulations for pins under ?vd3? (power supply group column in ?pin table?). note 3) regulations for pins under ?vd5? (power supply group column in ?pin table?). items conditions symbol min. typ. max. unit note low level output voltage i ol =100 av ol 0 0.2 v 1, 2 power supply group ?vd3? output and i/o pins (except xout pin) i ol =2ma v ol 0 0.4 v 1, 2 i ol =100 av ol 0 0.2 v 1, 3 power supply group ?vd5? output and i/o pins i ol =4ma v ol 0 0.4 v 1 high level output voltage i oh = -100 av oh v dd33 -0.2 v dd33 v 1, 2 power supply group ?vd3? output and i/o pins (except xout pin) i oh = -2ma v oh 2.4 v dd33 v 1, 2 i oh = -100 av oh v dd5 -0.2 v dd5 v 1, 3 power supply group ?vd5? output and i/o pins i oh = -4ma v oh v dd5 0.8 v dd5 v 1, 3 note 1) values based on vss(gnd)=0v. note 2) regulations for pins under ?vd3? (power supply group column in ?pin table?). note 3) regulations for pins under ?vd5? (power supply group column in ?pin table?). items conditions symbol min. typ. max. unit note input leakage current i li -10 +10 a output leakage current i lo -25 +25 a items symbol min. typ. max. unit input pin capacitance c i 10 pf output pin capacitance c o 10 pf input-output pin capacitance c io 10 pf items symbol min. typ max. unit note analog video input voltage (vinp pin) v vinp 1.25 1.4 vp-p 1 note 1) the above maximum values are for the setting of ?r#28: adcgain=2'b00.?
YGV639 23 ac characteristics measurement conditions input voltage 0v / v dd33 input transition time 1ns (transition time is specified between v dd33 0.2 and v dd33 0.8.) measurement reference voltage: input v il /v ih output v dd33 /2v output load capacitance 20pf clock input no. items symbol min. typ. max. unit note xin clock frequency f xin 6 40 mhz 1 xin clock cycle time t xin 25 166 ns dtckin clock frequency f dtckin 40 mhz 2 dtckin clock cycle time t dtckin 25 ns 3 xin, dtckin clock high level pulse width t whclk 7.5 ns 4 xin, dtckin clock low level pulse width t wlclk 7.5 ns syclk clock frequency f syclk 83.16 mhz 1 5 syclk clock cycle time t syclk 12.03 ns 1 pll out clock frequency f pllo 252 332.64 mhz 1 6 pll out clock cycle time t pllo 3.01 3.96 ns 1 dclk clock frequency f dclk 40 mhz 2 7 dclk clock cycle time t dclk 25 ns 2 note 1) syclk is a 1/4 frequency divided internal clock of pll out. note 2) dclk is a dot clock that is used internally. 0.5v dd 34 v ih v il 1, 2
YGV639 24 power supply and reset input no. items symbol min. typ. max. unit note 1 reset_n pin input time t wres 10 s 1 2 cpu access stand-by time after reset_n negation t waw 10 to 67 ms 3 reset_n setup time t sres 0 ns 2 4 power-on time difference (vdd33, vddin, avdd) t vskwr 1 s 3 5 power-off time difference (vdd33, vddin, avdd) t vskwf 1 s 4 6 power rise time t vrise 200 ms 7 vdd5power-on/off time difference t vskwc -1 s 5 8 core power vout18 rise time t vcore 300 s 6 9 ocpen pin input time (initialization) t wocpe 10 s 10 ocpen pin low input time (abnormal) t wocpr 0.4 10 ms note 1) this is the time from when the following thr ee conditions are met to the time when reset_n rises: the voltage of the last power supply that was powered on reached at 3.0v, vout18 reached at 1.7v, and an input clock to xin pin becomes stable. note 2) this is the specification of the first power su pply that was powered up, out of vdd33, vddin, and avdd. note 3) it is recommended vdd33, vddin, and avdd be turned on simultaneously. if one second or more time-difference occurs it may have an adverse effect on lsi's reliability. note 4) it is recommended vdd33, vddin, and avdd be turned off simultaneously. if it takes more than one second, it may have an adverse effect on lsi's reliability. note 5) it is possible to shutdown 3v power supply (vdd33, vddin, and avdd) with 5v power (vdd5) applied. note 6) this is the value with four capacitors of 4.7 f connected to vout18 and vddcore pins. vdd5 vdd33 vddin avdd vout18 reset_n cs_n xin vdd33 avdd vdd5 3.0 v (vdd5=3.3v) 4.75v (vdd5=5.0v) 6 3.0v (vdd5=3.3v) 4.75v (vdd5=5.0v) 3.0 v 3.0v 1.65v 4 6 6 3.0 v 2 1 3 1 2 5 7 3.0v 7 1.7 v 1 1
YGV639 25 1.7 v 1.7 v 8 2.0 v ocpen vout18 vddin ocp _ n 8 vout18 shorted vout18 shorted 10 10 9 power-up temporal power short-circuiting continual power short-circuiting cpu detected an unusual condition return processing confirmation of normal return cpu detected an unusual condition return processing confirmation of a continuing unusual condition reset _ n 1 1
YGV639 26 cpu interface parallel interface no. item code min. typ. max. unit note 1 ps2-0: setup time t sa 4 1 2 ps2-0: hold time t ha 0 1 3 cs_n: setup time t scs 0 2 4 cs_n: hold time t hcs 0 2 5 d7-0: output data turn on time t ond 0 6 d7-0: output data turn off time t offd 30 7 d7-0: output data valid delay time t dd 0 8 d7-0: output data hold time t hd 0 9 wait_n, ready_n: turn on time t onwait 0 10 wait_n, ready_n: valid delay time t dwait 25 11 wait_n, ready_n: turn off time t offwait 30 12 d7-0: input data setup time t sd t syclk +15 13 d7-0: input data hold time t hd 2 14 ready_n: hold time t hready 0 30 15 command pulse active time t acmd 2t syclk 3 16 command pulse inhibit time t icmd 4t syclk 3 17 command cycle time t ccmd 6t syclk ns 3 note 1) regulations for wr_n and rd_n signals; however, in cs_n control, there are regulations for cs_n. note 2) conditions that prove to be wr_n and rd_n c ontrols. if these conditions are not met, these are for cs_n control. note 3) ?command pulse? means a low active pulse obtained by performing or operation between cs_n signal and each of wr_n and rd_n signals. i) cpu read cycle ps2-0 cs_n rd_n d7-0 wait_n ready_n 1 4 2 5 3 6 9 711 10 8 hi-z hi-z hi-z hi-z 9 711 hi-z hi-z 14
YGV639 27 ii) cpu write cycle ps2-0 cs_n wr_n d7-0 wait_n ready_n 1 4 2 12 3 13 11 9 hi-z hi-z 9 11 10 hi-z hi-z 14 iii) access cycle cs_n wr_n rd_n 15 16 17 15 16 17 15 16 17 15 16 17
YGV639 28 serial interface chip select no. items symbol min. typ. max. unit note 1 sclk clock cycle time t wsclk 200 1 2 sclk clock high level pulse width t whsclk 100 1 3 sclk clock low level pulse width t wlsclk 100 1 4 scs_n: setup time t sscs 25 5 scs_n: hold time t hscs 25 6 sdin: setup time t ssdi 25 7 sdin: hold time t hsdi 25 8 sdout: output data delay time t dsdo 100 2 9 sdout: turn off time t offfsdo 20 10 scs_n: pulse inhibit time t iscs 400 ns note 1) in the initialization, the 2-divided clock of xin is used for the system clock. and, sclk is sampled twice by the system clock. therefore, the minimum value of t wsclk becomes xin cycle8 (t xin 8), and minimum values of t whsclk and t wlsclk become xin cycle 4 (t xin 4). compare it with the value defined in the above tabl e and use the larger value. note 2) in the initialization, the maximum value of t dsdo becomes xin cycle 6+100ns (t xin 6 + 100ns). scs_n sclk sdin sdout hi-z 1 4 3 2 6 7 5 8 9 8 scs_n sclk 10
YGV639 29 pattern memory interface no. items symbol min typ. max unit note 1 ma25-0: output delay time from syclk t dma 14 1 2 moe_n: output delay time from syclk t doe 2 14 1 3 mwe_n: output delay time from syclk t dwe 2 14 1 4 md15-0 : input setup time to syclk t smd 4 1 5 md15-0 : input hold time from syclk t hmd 0 1 6 md15-0 : output delay time from syclk t dmd 24 1 7 ma25-0: hold time from moe_n t hmar 0 8 md15-0 : input hold time from moe_n, ma25-0 t hmdi 0 9 ma25-0: hold time from mwe_n t hmaw 0 10 md15-0 : hold time from mwe_n t hmdo 1 11 md15-0 : turn off time from mwe_n t offmdo 1 10 12 output turn off/on time from rahz_n t on/offra 25 ns note 1) syclk is an internal clock. memory access cycle i) random read cycle syclk ma25-0 moe_n mwe_n md15-0 1 4 5 3 2 1 2 7 8 note: after a read access, values of ma25-0, moe_n are held until the pattern memory is accessed again. ii) write cycle syclk ma25-0 moe_n mwe_n md15-0 1 6 2 3 1 3 9 11 10 note: after a write access, the valu e of ma25-0 is held until the pattern memory is accessed again.
YGV639 30 iii) rahz_n ma25-0,md15-0 moe_n,mwe_n rahz_n 12 12 note: the ac characteristics of an external memory connecting to vc1e must meet the following conditions. (the following conditions are the values converted from the ac characteristics of the vc1e pattern memory; they do not guarantee the following specifications directly. in addition, the item names below are those mainly for an externally-connected memory.) ?f?, ?r?, and ?p? in the below are as follows. f =(r#2:fltim[1:0]+1) number of floating clocks r =(r#3:rdm[3:0]+1) number of random access clocks, p =(r#3:pag[2:0]+1) number of page mode access clocks no. items conditions 13 address, access time it should be (f + r) * t syclk ? t dma (max) ? t smd (min) or lower 14 output enable time it should be r * t syclk ? t doe (max) ? t smd (min) or lower 15 page mode access time it should be p * t syclk ? t dma (max) ? t smd (min) or lower 16 data turn on time it should be 0[ns] or over 17 data turn off time it should be f * t syclk - t doe (max) + t dwe (min) or lower 18 data setup time it should be r * t syclk - t dmd (max) + t dwe (min) or lower syclk ma25-n ma(n-1)-0 moe_n mwe_n md15-0 13 17 15 7 8 14 10 18 tdma(max) tsmd(min) tdma(max) r f tdoe(max) tdwe(max) tdma(max) tdma(max) 8 tsmd(min) p 16 syclk ma25-n ma(n-1)-0 moe_n mwe_n md15-0 10 18 tdma(max) r f tdwe(max) tdwe(max) tdma(max) tdmd(max) tdoe(max)
YGV639 31 display timing signals no. items symbol min typ max unit note 1 dotclk: delay time t ddotc 26 ns 2 vsync_n, hcsync_n, blank_n, dr5-0, dg5-0, db5-0, clkv, starth, startv, loadh, pol, outenv: output hold time t hdisp -4 ns 3 vsync_n, hcsync_n, blank_n, dr5-0, dg5-0, db5-0, clkv, starth, startv, loadh, pol, outenv: output delay time t ddisp 4 ns dtckin or xin dotclk outputs 1 3 2 1 1 note: the above figure shows a state in which dotclk is not inverted.
YGV639 32 package outlines
YGV639 33

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